Structure and method for vertical tunneling field effect transistor with leveled source and drain

摘要

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

主权项

1. A semiconductor structure, comprising:
a semiconductor substrate having a first active region; a first semiconductor mesa formed on the semiconductor substrate within the first active region; a first resistor formed on the semiconductor substrate within the first active region, wherein the first resistor includes a first doped feature formed on the first semiconductor mesa and extended to the semiconductor substrate within the first active region; and a first contact and a second contact connected to two ends of to the first resistor, respectively, wherein the first contact lands on the semiconductor substrate and the second contact lands on the first semiconductor mesa, wherein the first doped feature formed on the first semiconductor mesa extends from the second contact to the semiconductor substrate, wherein the first doped feature has a same type of conductivity extending from the second contact to the semiconductor substrate.