发明名称 |
Multi-die DRAM banks arrangement and wiring |
摘要 |
A memory die for use in a multi-die stack having at least one other die. The memory die includes a plurality of contacts arranged in a field and configured to interface to the other dies of the multi-die stack. A first subset of the buffer lines of a number of buffer lines are connected to respective contacts in the field. The memory die also includes a number of buffers and cross-bar lines. The buffers are coupled between respective signal lines and respective buffer lines. The cross-bar lines interconnect respective pairs of buffer lines in a second subset of the buffer lines that is distinct from the first subset of the buffer lines. |
申请公布号 |
US9111588(B2) |
申请公布日期 |
2015.08.18 |
申请号 |
US201113885225 |
申请日期 |
2011.12.07 |
申请人 |
RAMBUS INC. |
发明人 |
Vogelsang Thomas |
分类号 |
G11C5/00;G11C5/06;G11C5/02;G11C8/12 |
主分类号 |
G11C5/00 |
代理机构 |
Morgan, Lewis & Bockius LLP |
代理人 |
Morgan, Lewis & Bockius LLP |
主权项 |
1. A memory die for use in a multi-die stack having at least one other die, comprising:
a plurality of memory banks, each having a plurality of signal lines; a plurality of contacts arranged in a field, the contacts configured to interface to the at least one other die of the multi-die stack; buffer lines, including a first subset of buffer lines and a second subset of buffer lines, the first subset of buffer lines being connected to respective contacts in the field; a plurality of buffers, each buffer of the plurality of buffers having a first terminal coupled to a respective signal line, a second terminal coupled to another buffer of the plurality of buffers, and a third terminal coupled to a respective buffer line; and a plurality of cross-bar lines interconnecting respective pairs of buffer lines in the second subset of buffer lines. |
地址 |
Sunnyvale CA US |