Process for enhanced 3D integration and structures generated using the same

摘要

An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

主权项

1. A 4DI structure comprising a first substrate placed in a horizontal orientation and attached to an assembly comprising a set of two or more second substrates bonded to each other and placed in a vertical orientation beneath said first substrate where there is an area array of electrical contacts between said first substrate and said second substrates and said area array of electrical contacts is formed by means of corner connections to wiring on the face of said set of second substrates, so that said corner connections electrically connect said second substrates.