Automatic pipeline stage insertion

摘要

The optimal configuration of a number of optional pipeline stages within the data paths of systems-on-chip is determined by application of a solver. The solver includes variables such as: the placement of modules physically within the floorplan of the chip; the signal propagation time; the logic gate switching time; the arrival time, after a clock edge, of a signal at each module port; the arrival time at each pipeline stage; and the Boolean value of the state of activation of each optional pipeline stage. The optimal configuration ensures that a timing constraint is met, if possible, with the lowest possible cost of pipeline stages.

主权项

1. A method of configuring optional pipeline stages within a system on a chip, the system comprising modules where each module includes one or more optional pipeline stages, the method comprising the steps of:
determining a unit cost for each optional pipeline stage; determining a timing delay for each configuration of activated optional pipeline stages in a plurality of configurations, wherein each configuration of activated optional pipeline stages is such that for each module at most only one of the optional pipeline stages within that module is activated; and using a solver to find a system configuration of activated optional pipeline stages among the plurality of configurations that meets a constraint on the timing delay to minimize a total cost, the total cost including the unit cost for each activated optional pipeline stage.