Input/output delay testing for devices utilizing on-chip delay generation

摘要

I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

主权项

1. An apparatus comprising:
a plurality of I/O buffer circuits, each of the plurality of buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the respective buffer circuit; and testing circuitry for the loop-back testing for the plurality of buffer circuits, the loop-back testing including determining whether test data transmitted by the transmitter of each buffer circuit matches test data received by the respective coupled receiver; wherein the testing circuitry includes:
a delay line to provide a plurality of delay values from a transmit clock signal for the testing of the plurality of buffer circuits,a counter to provide a count to choose one of the plurality of delay values of the delay line as a current delay value for the delay line, wherein the counter provides for one of:
multiple sweeps of delay values for loop-back testing, the sweeps including a first sweep of delay values wherein the counter counts down to decrease the current delay value from a first initial delay value until a first result occurs at a first delay value and a second sweep of delay values wherein the counter counts up to increase the current delay value from a second initial delay value until a second result occurs at a second delay value; ora single sweep of delay values for loop-back testing wherein the counter counts down to decrease the current delay value from the first initial delay value, the single sweep including determining that a first result occurs at a first delay value, the single sweep counting down until a second result occurs at a second delay value, andtest logic for the loop-back testing, wherein the test logic is to determine whether results of the loop-back testing for each of the buffer circuits are matches or mismatches, the test logic including a first logic configured to determine whether or not all results of the loop-back testing for the plurality of buffer circuits are matches for the current delay value and a second logic configured to determine whether or not all results of the loop-back testing for the plurality of buffer circuits are mismatches for the current delay value; wherein the apparatus is to determine a difference between the first delay value and the second delay value, the first delay value being identified using the first logic and the second delay value being identified using the second logic.