Memory system

摘要

A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different resistance states; and an access circuit operative to execute a write sequence of changing the resistance state for writing data in the memory cell, wherein the access circuit, on the write sequence, executes a first step of changing all memory cells provided at the intersections of access first lines and the access and fault second lines to the high resistance state, and a second step of changing all or part of access cells connected to the access second line to the low resistance state.

主权项

1. A memory system, comprising:
a cell array including a unit cell array, said unit cell array containing plural first lines, plural second lines intersecting said plural first lines, and plural memory cells provided at the intersections of said plural first lines and said plural second lines and operative to store data in accordance with different resistance states; and an access circuit operative to execute a write sequence of changing said resistance state for writing data in said memory cell, wherein said memory cell has two resistance states including a low resistance state and a high resistance state at least, an access-targeted memory cell is defined as an access cell, a first line connected to said access cell as an access first line, a second line connected to said access cell as an access second line, a fault-caused memory cell as a fault cell, and a second line connected to said fault cell as a fault second line, said access circuit, on said write sequence, executes a first step of changing all memory cells provided at the intersections of access first lines and said access and fault second lines to said high resistance state, and a second step of changing all or part of access cells connected to said access second line to said low resistance state, and said access circuit, on said write sequence, once changes said access cell which is changed to said low resistance state on said second step to said high resistance state on said first step.