发明名称 Differential sense amplifier without dedicated precharge transistors
摘要 The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.
申请公布号 US9111593(B2) 申请公布日期 2015.08.18
申请号 US201213456057 申请日期 2012.04.25
申请人 Soitec 发明人 Ferrant Richard;Thewes Roland
分类号 G11C7/00;G11C7/06;G11C7/12;G11C11/4091;G11C11/4094 主分类号 G11C7/00
代理机构 代理人 Holman Jeffrey T.
主权项 1. A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including: a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line, with each CMOS inverter comprising: a pull-up transistor having a drain and a source, with the source coupled to a pull-up voltage source, anda pull-down transistor having a drain and a source, with the source coupled to a pull-down voltage source,with the pull-up transistor and the pull-down transistor of each CMOS inverter having a common drain, wherein the sense amplifier has a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines to precharge the first and second bit lines to a precharge voltage, wherein the precharge transistors are constituted by the pull-up transistors or by the pull-down transistors, and the precharge transistors are configured to operate in a precharge state in response to operation of the pull-up source or the pull-down source at a partial voltage level.
地址 Bernin FR