Memory device

摘要

A memory device including a training circuit, a data strobe transmission path, data transmission paths, data latching circuits and a phase detection circuit is provided. When the memory device is under a training mode, a training process is performed on at least one of the data transmission paths. The phase detection circuit detects a phase difference between signals between the data transmission path and the data strobe transmission path to adjust a delay time of the adjustable delay circuit of the data transmission path until the signals are in phase. When the memory device is under an operation mode, each of the data latching circuits receives a treed data strobe signal from the data strobe transmission path to latch a delayed data signal received from the adjustable delay circuit of one of the data transmission paths.

主权项

1. A memory device, comprising:
a training circuit; a data strobe transmission path comprising:
a first input path having a first input connected to the training circuit and an external data strobe signal source; anda tree circuit connected to a first output of the first input path; a plurality of data transmission paths each comprising:
a second input path having a second input connected to an external data signal source, and the second input of the second input path of at least one of the data transmission paths is further connected to the training circuit; andan adjustable delay circuit connected to a second output of the second input path; a plurality of data latching circuits each connected to outputs of the adjustable delay circuit of one of the data transmission paths and the tree circuit; a phase detection circuit connected to the outputs of the adjustable delay circuit of at least one of the data transmission paths and the tree circuit; and wherein when the memory device is under a training mode, a training process is performed on at least one of the data transmission paths such that the training circuit is activated to generate a training clock signal to both of the first input path and the second input path and further to the tree circuit and the adjustable delay circuit to generate a first clock signal and a second clock signal respectively, wherein the phase detection circuit detects a phase difference between the first clock signal and the second clock signal to adjust a delay time of the adjustable delay circuit until the first clock signal and the second clock signal are in phase; wherein when the memory device is under an operation mode, the training circuit is deactivated such that the first input path receives an external data strobe signal to generate a data strobe signal to the tree circuit and the second input path receives an external data signal to generate a data signal to the adjustable delay circuit, wherein each of the data latching circuits receives a treed data strobe signal from the tree circuit to latch a delayed data signal received from the adjustable delay circuit of one of the data transmission paths.