1588 deterministic latency with gearbox

摘要

Systems and methods are disclosed for precisely determining the delay between data being received at the pins of a circuit and being processed by gearbox circuitry, to being processed by a time-stamp unit of the circuit. In an exemplary embodiment, the gearbox circuitry may output a data valid signal which may be monitored by the time-stamp unit. By monitoring the data valid signal, the time-stamp unit may synchronize a local state machine with the internal state of the gearbox circuitry and thus determine the total delay through the combined processing circuitry with high accuracy.

主权项

1. A system for measuring a delay, the system comprising:
a pin operative to receive data; gearbox circuitry operative to convert the received data to parallel data and output the parallel data, wherein the gearbox circuitry is coupled to the pin; and processing circuitry coupled to the gearbox circuitry, wherein the processing circuitry is operative to:
receive the parallel data; anddetermine, based at least in part on a determined state of a plurality of states of the gearbox circuitry, a value of the delay between the data being received at the pin and the parallel data being received at the processing circuitry, wherein the determined state of the plurality of states of the gearbox circuitry is determined by evaluating a temporal sequence of values of a data valid signal.