Method for producing a semiconductor device having SGTS

摘要

In a method for producing a semiconductor device, Si pillars that include i-layers, N+ regions that serve as lower impurity regions, N+ regions and a P+ region that serve as upper impurity regions, and i-layers are formed by using SiO2 layers as an etching mask. Thus, surrounding gate MOS transistors (SGTs) are produced in which the upper impurity regions and the lower impurity regions respectively function as impurity layers constituting a source or a drain of the SGTs formed in upper portions and lower portions of the Si pillars.

主权项

1. A method for producing a semiconductor device having surrounding gate MOS transistors (SGTs), the method comprising:
a first impurity-region-forming step of forming one or both of a first impurity region containing a donor impurity and a second impurity region containing an acceptor impurity in a single layer in a surface layer portion of a semiconductor substrate; a first semiconductor-layer-forming step of forming a first semiconductor layer above the semiconductor substrate; a second impurity-region-forming step of forming one or both of a third impurity region containing a donor impurity and a fourth impurity region containing an acceptor impurity in a single layer in a surface layer portion of the first semiconductor layer; a second semiconductor-layer-forming step of forming a second semiconductor layer above the first semiconductor layer; an island-shaped semiconductor-forming step of etching the second semiconductor layer, the first semiconductor layer, and the semiconductor substrate from an upper surface of the second semiconductor layer to form a plurality of first island-shaped semiconductors each of which includes the semiconductor substrate, the first semiconductor layer, and the second semiconductor layer and in which the first impurity region and the second impurity region are overlapped with one or other of the third impurity region and the fourth impurity region in a perpendicular direction with respect to a surface of the semiconductor substrate; a third impurity-region-forming step of forming a fifth impurity region containing a donor impurity in a bottom portion of a first island-shaped semiconductor having the first impurity region and forming a sixth impurity region containing an acceptor impurity in a bottom portion of a first island-shaped semiconductor having the second impurity region; a gate insulating layer-forming step of forming a gate insulating layer so as to surround the first island-shaped semiconductors; a gate conductor layer-forming step of forming a gate conductor layer so as to surround the gate insulating layer; and a fourth impurity-region-forming step of forming a seventh impurity region containing a donor impurity in a top portion of the first island-shaped semiconductor having the third impurity region and forming an eighth impurity region containing an acceptor impurity in a top portion of the first island-shaped semiconductor having the fourth impurity region, the top portions being located above the gate insulating layer and the gate conductor layer, wherein one or both of a first SGT and a second SGT are formed on the lower portion side of the first island-shaped semiconductors, the first SGT including the first impurity region and the fifth impurity region, one of which functions as a source and the other of which functions as a drain, the semiconductor substrate of the first island-shaped semiconductor which functions as a channel, and the gate conductor layer which functions as a gate, the second SGT including the second impurity region and the sixth impurity region, one of which functions as a source and the other of which functions as a drain, the semiconductor substrate of the first island-shaped semiconductor which functions as a channel, and the gate conductor layer which functions as a gate, and one or both of a third SGT and a fourth SGT are formed on the upper portion side of the first island-shaped semiconductors, the third SGT including the third impurity region and the seventh impurity region, one of which functions as a source and the other of which functions as a drain, the second semiconductor layer of the first island-shaped semiconductor which functions as a channel, and the gate conductor layer which functions as a gate, the fourth SGT including the fourth impurity region and the eighth impurity region, one of which functions as a source and the other of which functions as a drain, the second semiconductor layer of the first island-shaped semiconductor which functions as a channel, and the gate conductor layer which functions as a gate.