发明名称 |
Technique for improving the performance of a tessellation pipeline |
摘要 |
A tessellation pipeline includes an alpha phase and a beta phase. The alpha phase includes pre-tessellation processing stages, while the beta phase includes post-tessellation processing stages. A processing unit configured to implement a processing stage in the alpha phase stores input graphics data within a buffer and then copies over that buffer with output graphics data, thereby conserving memory resources. The processing unit may also copy output graphics data directly to a level 2 (L2) cache for beta phase processing by other tessellation pipelines, thereby avoiding the need for fixed function copy-out hardware. |
申请公布号 |
US9111360(B2) |
申请公布日期 |
2015.08.18 |
申请号 |
US201313829501 |
申请日期 |
2013.03.14 |
申请人 |
NVIDIA CORPORATION |
发明人 |
Hakura Ziyad S.;Wang Zhenghong |
分类号 |
G06T1/20 |
主分类号 |
G06T1/20 |
代理机构 |
Artegis Law Group, LLP |
代理人 |
Artegis Law Group, LLP |
主权项 |
1. A graphics subsystem configured to implement a graphics processing pipeline that includes a first set of processing stages and a second set of processing stages, the graphics subsystem comprising:
a first processing engine configured to:
retrieve graphics object data from a first memory unit;perform a first graphics processing operation on the graphics object data at a first processing stage included in the first set of processing stages to generate processed graphics object data;determine that the first processing stage is the final processing stage in the first set of processing stages;copy the processed graphics object data to a second memory unit that is accessible by one or more processing engines that are configured to implement the second set of processing stages;perform a second graphics processing operation on the processed graphics object data to generate reduced graphics object data; andcopy the reduced graphics object data to the first memory unit. |
地址 |
Santa Clara CA US |