Read margin measurement in a read-only memory

摘要

Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit.

主权项

1. A programmable non-volatile memory, comprising:
an array of memory cells arranged in rows and columns, each memory cell comprising:
a floating-gate transistor having a source/drain path and a floating gate electrode;a precharge transistor, having a source/drain path connected to the source/drain path of the floating-gate transistor at a sense node, and having a gate receiving a precharge signal; anda select transistor, having a source/drain path connected in series with the source/drain paths of the floating-gate transistor and the precharge transistor between a first array power supply voltage and a second array power supply voltage, and having a gate receiving a word line; a read circuit, coupled to the sense node of a memory cell, and having an output; and a circuit, coupled to the output of the read circuit, for developing a voltage responsive to the output of the read circuit over a sequence of read cycles applied to a selected one of the memory cells.