发明名称 Methods and apparatus of wafer level package for heterogeneous integration technology
摘要 Methods and apparatus are disclosed to form a WLP device that comprises a first chip made of a first technology, and a second chip made of a second technology different from the first technology packaged together by a molding material encapsulating the first chip and the second chip. A post passivation interconnect (PPI) line may be formed on the molding material connected to a first contact pad of the first chip by a first connection, and connected to a second contact pad of the second chip by a second connection, wherein the first connection and the second connection may be a Cu ball, a Cu via, a Cu stud, or other kinds of connections.
申请公布号 US9111949(B2) 申请公布日期 2015.08.18
申请号 US201213536549 申请日期 2012.06.28
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Yu Chen-Hua;Yeh Der-Chyang
分类号 H01L23/48;H01L21/60;H01L21/56;H01L23/00;H01L23/498;H01L23/538;H01L25/065;H01L25/16;H01L25/00;H01L23/31;H01L21/683;H01L23/64;H01L25/18 主分类号 H01L23/48
代理机构 Slater & Matsil, L.L.P. 代理人 Slater & Matsil, L.L.P.
主权项 1. A device comprising: a first chip made of a first technology having a first contact pad, the first chip having a first passivation layer over a top surface of the first chip and the first contact pad, the first passivation layer having a bottom surface in contact with the top surface of the first chip and the first contact pad, and having a top surface opposite the bottom surface of the first passivation layer, wherein a first opening in the first passivation layer exposes the first contact pad; a second chip made of a second technology different from the first technology having a second contact pad, the second chip having a second passivation layer over a top surface of the second chip and the second contact pad, the second passivation layer having a bottom surface in contact with the top surface of the second chip and the second contact pad, and having a top surface opposite the bottom surface of the passivation layer, wherein a second opening in the second passivation layer exposes the second contact pad; a molding material encapsulating the first chip and the second chip, the molding material extending over the top surface of the first passivation layer and over the top surface of the second passivation layer; a first connection mounted on, and aligned directly over, the first contact pad; a second connection mounted on, and aligned directly over, the second contact pad; an insulating layer formed over the molding material and over the first and second connections, the insulating layer having openings exposing the first and second connections; and a post passivation interconnect (PPI) line on the insulating layer connected to the first contact pad by the first connection and connected to the second contact pad by the second connection; wherein the first connection is of a first connection mechanism type and the second connection is of a second connection mechanism type different from the first connection mechanism type, both connection mechanism types selected from a group consisting essentially of a conductive ball, a conductive via, or a conductive stud.
地址 Hsin-Chu TW