| 发明名称 | Multilayer pillar for reduced stress interconnect and method of making same | ||
| 摘要 | A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions. | ||
| 申请公布号 | US9111816(B2) | 申请公布日期 | 2015.08.18 |
| 申请号 | US201213431609 | 申请日期 | 2012.03.27 |
| 申请人 | INTERNATIONAL BUSINESS MACHINES CORPORATION | 发明人 | Jadhav Virendra R.;Semkow Krystyna W.;Srivastava Kamalesh K.;Sundlof Brian R. |
| 分类号 | H01L23/48;H01L23/52;H01L29/40;H01L23/00 | 主分类号 | H01L23/48 |
| 代理机构 | Roberts Mlotkowski Safran & Cole, P.C. | 代理人 | Meyers Steven;Roberts Mlotkowski Safran & Cole, P.C. |
| 主权项 | 1. A structure comprising a modulated copper pillar including: an uppermost layer that connects the modulated copper pillar to a chip and that prevents diffusion of materials between the chip and materials of the modulated copper pillar; an upper copper layer; at least one low strength, high ductility deformation region; and a lower copper layer, wherein the at least one low strength, high ductility deformation region is configured to absorb force imposed during chip assembly and thermal excursions, wherein the at least one low strength, high ductility deformation region comprises at least two separate, low strength, high ductility deformation layers of the modulated copper pillar. | ||
| 地址 | Armonk NY US | ||