发明名称 STRESSED CHANNEL BULK FIN FIELD EFFECT TRANSISTOR
摘要 Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.
申请公布号 US2015228789(A1) 申请公布日期 2015.08.13
申请号 US201414178990 申请日期 2014.02.12
申请人 Kabushiki Kaisha Toshiba ;International Business Machines Corporation 发明人 Basker Veeraraghavan S.;Hokazono Akira;Itokawa Hiroshi;Yamashita Tenko;Yeh Chun-chen
分类号 H01L29/78;H01L21/8234;H01L27/088 主分类号 H01L29/78
代理机构 代理人
主权项 1. A semiconductor structure comprising: a single crystalline material layer located in a substrate; a plurality of semiconductor fins located on a top surface of said single crystalline material layer; at least one dielectric material portion located on said top surface of said single crystalline material layer and laterally contacting bottom portions of said plurality of semiconductor fins; a gate structure including a vertical stack of a gate dielectric and a gate electrode and contacting a top surface of each of said at least one dielectric material portion and sidewalls of said plurality of semiconductor fins; and a gate spacer laterally contacting sidewalls of said gate structure and sidewalls of said at least one dielectric material portion and a top surface of said single crystalline material layer.
地址 Tokyo JP