发明名称 STANDARD CELL GLOBAL ROUTING CHANNELS OVER ACTIVE REGIONS
摘要 An integrated circuit chip includes CMOS integrated circuit cells arranged in a semiconductor layer, each including first and second active regions, having first and second polarities, respectively. A first power rail is routed along boundaries of the CMOS integrated circuit cells proximate to the first active regions. A second power rail is routed over second active regions. Global routing channels are routed over the second active regions such that the second power rail is disposed between the global routing channels and the first power rail. The global routing channels are coupled between the CMOS integrated circuit cells to couple the CMOS integrated circuit cells together globally in the integrated circuit chip.
申请公布号 US2015228650(A1) 申请公布日期 2015.08.13
申请号 US201414175847 申请日期 2014.02.07
申请人 OMNIVISION TECHNOLOGIES, INC. 发明人 Sun Tianjia;Li Lingchuan;Wu Shumin
分类号 H01L27/092;H01L23/528 主分类号 H01L27/092
代理机构 代理人
主权项 1. An integrated circuit chip, comprising: a plurality of complementary metal oxide semiconductor (CMOS) integrated circuit cells arranged in a semiconductor layer, wherein each one of the CMOS integrated circuit cells includes first and second active regions disposed in the semiconductor layer, wherein the first active region is doped with dopants having a first polarity, and wherein the second active region is doped with dopants having a second polarity; a first power rail included in metal layers disposed over the semiconductor layer and routed along boundaries of the CMOS integrated circuit cells proximate to the first active regions of the CMOS integrated circuit cells; a second power rail included in the metal layers disposed over the semiconductor layer and routed over second active regions of the CMOS integrated circuit cells; and global routing channels included in the metal layers over the semiconductor layer and routed over the second active regions of the CMOS integrated circuit cells such that the second power rail is disposed the metal layers between the global routing channels and the first power rail, wherein the global routing channels are coupled between the CMOS integrated circuit cells to couple the CMOS integrated circuit cells together globally in the integrated circuit chip.
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