发明名称 |
MULTI-VIA INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURE |
摘要 |
An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure. |
申请公布号 |
US2015228584(A1) |
申请公布日期 |
2015.08.13 |
申请号 |
US201414257759 |
申请日期 |
2014.04.21 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Huang Yu-Fei;Li Ming Xiang;Wan Edward;Chen Jacob;Yaung Dun-Nian;Chen Cheng-Eng Daniel |
分类号 |
H01L23/538;H01L25/065;H01L25/00;H01L21/768 |
主分类号 |
H01L23/538 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus comprising:
a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first metal lines formed in the first dielectric layers over the first substrate, wherein the first substrate has a thickness less than about 5 μm; a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second metal lines formed in the second dielectric layers over the second substrate; and a plurality of multi-via interconnect structures, a first multi-via interconnect structure extending from a second surface of the first semiconductor chip to a first one of the plurality of first metal lines in the first semiconductor chip and to a second one of the plurality of second metal lines in the second semiconductor chip. |
地址 |
Hsin-Chu TW |