发明名称 NONVOLATILE RANDOM ACCESS MEMORY
摘要 According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.
申请公布号 US2015228320(A1) 申请公布日期 2015.08.13
申请号 US201514692239 申请日期 2015.04.21
申请人 SHIRAI Yutaka;SHIMIZU Naoki;TSUCHIDA Kenji;WATANABE Yoji;BAE Ji Hyae;KIM Yong Ho 发明人 SHIRAI Yutaka;SHIMIZU Naoki;TSUCHIDA Kenji;WATANABE Yoji;BAE Ji Hyae;KIM Yong Ho
分类号 G11C8/18;G11C8/10 主分类号 G11C8/18
代理机构 代理人
主权项 1. A nonvolatile random access memory comprising: a memory cell array including banks, each bank including rows; first word lines formed in one-to-one correspondence with the rows; an address latch circuit configured to latch a first row address signal; a row decoder configured to activate one of the first word lines; a clock generator configured to generate an internal clock signal; and a control circuit configured to receive a first command based on a high edge of one clock cycle of the internal clock signal, and receive a second command based on a low edge of the one clock cycle.
地址 Seongnam KR