| 发明名称 |
SYSTEM AND METHOD FOR IMPROVING ECC ENABLED MEMORY TIMING |
| 摘要 |
A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves. |
| 申请公布号 |
US2015227488(A1) |
申请公布日期 |
2015.08.13 |
| 申请号 |
US201514695595 |
申请日期 |
2015.04.24 |
| 申请人 |
Texas Instruments Incorporated |
发明人 |
Langadi Saya Goud |
| 分类号 |
G06F13/42;G06F11/10 |
主分类号 |
G06F13/42 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A pipeline communication system comprising:
a master and a plurality of slaves configured to communicate with each other, each of the plurality of slaves comprising a memory, and being configured to generate a first ready signal and a second ready signal, wherein the first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves, wherein the second ready signal is generated independent of the error check in each of the plurality of slaves. |
| 地址 |
Dallas TX US |
