Completion Time Determination for Vector Instructions

摘要

In an embodiment, a processor may include a completion time determination circuit. The completion time determination circuit may be configured to receive one or more source operands of a vector memory operation used to produce the addresses of the vector elements accessed by the vector memory operation. The completion time determination circuit may be configured to determine a completion time for the vector memory operation (e.g. based on a number of TLB accesses, a number of cache accesses, and/or other aspects of the vector memory operation). The completion time determination circuit may provide the completion time to an issue circuit, which may use the completion time to schedule operations dependent on the vector memory operation, if any.

主权项

1. A processor comprising:
an issue circuit coupled to receive a vector memory operation to be executed in the processor, wherein the issue circuit is configured to issue the vector memory operation responsive to dependencies on source operands resolving for the vector memory operation; and a completion time determination circuit coupled to receive the source operands of the vector memory operation, wherein the completion time determination circuit is configured to determine, responsive to the source operands, a time at which the vector memory operation will complete; wherein the issue circuit is coupled to the completion time determination circuit to receive an indication of the time, wherein the issue circuit is configured to schedule one or more operations that are dependent on the vector memory operation responsive to the indication of the time determined by the completion time determination circuit.