| 发明名称 |
MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS |
| 摘要 |
A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor. |
| 申请公布号 |
US2015228334(A1) |
申请公布日期 |
2015.08.13 |
| 申请号 |
US201514692677 |
申请日期 |
2015.04.21 |
| 申请人 |
Crossbar, Inc. |
发明人 |
NAZARIAN Hagop;JO Sung Hyun;LU Wei |
| 分类号 |
G11C13/00 |
主分类号 |
G11C13/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A non-volatile memory device, comprising: a word line extending along a first direction:
a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one resistive memory cell comprising a resistive memory device in series with a selector device, and a select transistor, the resistive memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. |
| 地址 |
Santa Clara CA US |
