发明名称 METHOD FOR STEERING DMA WRITE REQUESTS TO CACHE MEMORY
摘要 A system may include a processor which may include a cache memory and a Direct Memory Access (DMA) controller, a peripheral device on an I/O expansion bus, and a bus interface coupled to the I/O expansion bus and the processor. The bus controller may determine if data packets sent from the peripheral device to the processor include a DMA write instruction to the cache memory with an optional desired cache location. Upon determining a DMA write instruction to the cache memory is included in the data packet, the bus controller may format the data in the data packet for storage in the cache and either receive the desired cache location or determine an appropriate location within the cache to store the formatted data. The bus controller may determine an alternate location within the cache if the desired location within the cache cannot accept more data from the peripheral device.
申请公布号 US2015227312(A1) 申请公布日期 2015.08.13
申请号 US201414178626 申请日期 2014.02.12
申请人 Oracle International Corporation 发明人 Feehrer John R.;Kurth Hugh R.;Silverton Aron J.;Stabile Patrick
分类号 G06F3/06 主分类号 G06F3/06
代理机构 代理人
主权项 1. An apparatus, comprising: a bridge unit configured to: receive a transaction packet on a communications bus, wherein the transaction packet includes a header and a data payload; anddetermine if the header of the received transaction packet identifies a preferred destination in a cache memory of a processor, responsive to a determination the header indicates a Direct Memory Access (DMA) write instruction to the cache memory; and a processor interface unit coupled to the bridge unit, wherein the processor interface is configured to: format the data payload of the received transaction packet for storage in the cache memory responsive to the determination the header indicates the DMA write instruction to the cache memory;select the preferred destination in the cache memory as a target destination for the DMA write instruction responsive to receiving a notification from the processor that the preferred destination in the cache memory can accept more data; andsend the formatted data payload to the processor with instructions to store the formatted data payload in the target destination.
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