发明名称 DYNAMIC CLOCK AND VOLTAGE SCALING WITH LOW-LATENCY SWITCHING
摘要 Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.
申请公布号 WO2015120199(A1) 申请公布日期 2015.08.13
申请号 WO2015US14688 申请日期 2015.02.05
申请人 QUALCOMM INCORPORATED 发明人 PAL, DIPTI RANJAN;PENZES, PAUL IVAN;ALLAM, MOHAMED WALEED
分类号 G06F1/32 主分类号 G06F1/32
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