发明名称 配線基板及びその製造方法
摘要 To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10. The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25. Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction. The solder resist layer 25 includes, within the opening portion 43, a side-surface covering portion 55 that covers the side surface of the connecting terminal portion 41 and a projecting wall portion 56 that is integrally formed with the side-surface covering portion 55 and disposed to project so as to intersect with the connection region 51.
申请公布号 JP5762376(B2) 申请公布日期 2015.08.12
申请号 JP20120208987 申请日期 2012.09.21
申请人 日本特殊陶業株式会社 发明人 林 貴広;永井 誠;森 聖二;西田 智弘;若園 誠;伊藤 達也
分类号 H01L23/12;H05K3/46 主分类号 H01L23/12
代理机构 代理人
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