发明名称 ルートi(√i)演算の保持を特徴とする基数8固定小数点FFT論理回路
摘要 A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.
申请公布号 JP5763911(B2) 申请公布日期 2015.08.12
申请号 JP20100272947 申请日期 2010.12.07
申请人 发明人
分类号 G06F7/00 主分类号 G06F7/00
代理机构 代理人
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