发明名称 Processor with virtualized instruction set architecture and methods
摘要 <p>Instructions for a digital data processing system comprise an operation code followed by data, which is dependent on the operation code. One operation code is followed by two register identifiers and a constant. If the register identifiers are in a first order, such as the smaller identifier preceding the larger, the instruction is interpreted as a branch if equal instruction. If the register identifiers are in the opposite order then the instruction is interpreted as a branch if not equal instruction. If the register identifiers are the same, then the operation is interpreted as an unconditional branch operation. The constant is used as the offset for a relative branch. Other pairs of commutative operations may also used with a different operation code. These may include arithmetic operations, such as addition and multiplication.</p>
申请公布号 GB2522990(A) 申请公布日期 2015.08.12
申请号 GB20140022101 申请日期 2014.12.12
申请人 IMAGINATION TECHNOLOGIES LIMITED 发明人 RANGANATHAN SUDHAKAR
分类号 G06F9/30 主分类号 G06F9/30
代理机构 代理人
主权项
地址