Output voltage variation reduction

摘要

A method of reducing voltage variations in a power supply may include generating an intermediate voltage and setting a first-transistor gate voltage at a first-transistor gate of a first transistor of the power supply based on the intermediate voltage. The method may also include setting an output voltage at an output node of the power supply based on a second-transistor gate voltage at a second-transistor gate of a second transistor. Additionally, the method may include setting the second-transistor gate voltage based on the first-transistor gate voltage such that the output voltage is based on the intermediate voltage, a first-transistor threshold voltage of the first transistor, and a second-transistor threshold voltage of the second transistor and such that variations in the first-transistor threshold voltage and the second-transistor threshold voltage at least partially cancel each other out.

主权项

1. A power supply comprising:
a reference node having a reference voltage; an intermediate node having an intermediate voltage; an output node having an output voltage; a voltage regulator configured to generate the intermediate voltage based on the reference voltage; a first transistor having a first-transistor threshold voltage and including a first-transistor source and a first-transistor gate, the first-transistor source communicatively coupled to the intermediate node such that a first-transistor gate voltage at the first-transistor gate is based on the intermediate voltage; and a second transistor having a second-transistor threshold voltage and including a second-transistor source and a second-transistor gate, the second-transistor source communicatively coupled to the output node such that the output voltage is based on a second-transistor gate voltage at the second-transistor gate, the second-transistor gate being communicatively coupled to the first-transistor gate such that the output voltage is based on the intermediate voltage, the first-transistor threshold voltage, and the second-transistor threshold voltage and such that variations in the first-transistor threshold voltage and the second-transistor threshold voltage at least partially cancel each other out; and a filter communicatively coupled between the first-transistor gate and the second transistor gate and configured to filter out noise associated with the intermediate voltage such that noise of the output voltage may be reduced with respect to the intermediate voltage; and a charge device configured to supply a charge voltage to the second-transistor gate to reduce a settling time of the filter; a comparator configured to compare a first-gate voltage of the first-transistor gate with a second-gate voltage of the second-transistor gate; and a logic module communicatively coupled to the comparator and the charge device and configured to turn off the charge device when the comparator indicates that the second-gate voltage is substantially equal to the first-gate voltage.