发明名称 High productivity combinatorial material screening for metal oxide films
摘要 Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) deposition, metal-based semiconductor (e.g. ZnOx, ZnSnOx, ZnInOx, or ZnGaOx) patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.
申请公布号 US9105526(B2) 申请公布日期 2015.08.11
申请号 US201314134571 申请日期 2013.12.19
申请人 Intermolecular, Inc. 发明人 Le Minh Huu;Lee Sang;Van Duren Jeroen
分类号 H01L21/16;H01L27/12;H01L21/02;H01L21/66 主分类号 H01L21/16
代理机构 代理人
主权项 1. A method for forming a plurality of thin film transistors on a substrate in a combinatorial manner, the method comprising: providing the substrate, wherein the substrate comprises a plurality of site-isolated regions, and wherein each site-isolate region further comprises one or more gate electrodes formed therein; depositing a gate dielectric layer above a surface of each site-isolated region; patterning the gate dielectric layer deposited above the surface of each site-isolated region; depositing a metal-based semiconductor layer above each gate dielectric layer, wherein the metal-based semiconductor layer comprises one of ZnOx, ZnSnOx, ZnInOx, or ZnGaOx; patterning the metal-based semiconductor layer deposited above the surface of each gate dielectric layer; depositing an etch stop layer above each metal-based semiconductor layer; patterning the etch stop layer deposited above each metal-based semiconductor layer; and depositing a source-drain layer above each etch stop layer; patterning the source/drain layer deposited above each etch stop layer, wherein the patterning the metal-based semiconductor layer is varied in the combinatorial manner between at least two of the plurality of site-isolated regions.
地址 San Jose CA US