发明名称 |
Sense amplifier |
摘要 |
A sense amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistive device, and a second resistive device. The first resistive device is coupled to a first data line and to a drain of the third transistor. The second resistive device is coupled to a second data line and to a drain of the fourth transistor. A terminal of the fifth transistor is coupled to the gate of the first transistor. A terminal of the sixth transistor is coupled to the gate of the second transistor. |
申请公布号 |
US9105312(B2) |
申请公布日期 |
2015.08.11 |
申请号 |
US201414177604 |
申请日期 |
2014.02.11 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
Hong Hyun-Sung |
分类号 |
G01R19/00;G11C7/06;H03F3/16;G11C7/12;G11C11/4091;G11C11/4094 |
主分类号 |
G01R19/00 |
代理机构 |
Lowe Hauptman & Ham, LLP |
代理人 |
Lowe Hauptman & Ham, LLP |
主权项 |
1. A sense amplifier circuit, comprising:
a first transistor and a second transistor, the first transistor and the second transistor being transistors of a first type; a third transistor and a fourth transistor, the third transistor and the fourth transistor being transistors of a second type; a first resistive device; a second resistive device; a fifth transistor; and a sixth transistor, wherein
a first end of the first resistive device is coupled to a first data line;a second end of the first resistive device is coupled to a drain of the third transistor and a gate of the second transistor;a first end of the second resistive device is coupled to a second data line;a second end of the second resistive device is coupled to a drain of the fourth transistor and a gate of the first transistor;a first terminal of the fifth transistor is coupled to a source of the third transistor;a second terminal of the fifth transistor is coupled to the first data line;a third terminal of the fifth transistor is coupled to the gate of the first transistor;a first terminal of the sixth transistor is coupled to a source of the fourth transistor;a second terminal of the sixth transistor is coupled to the second data line; anda third terminal of the sixth transistor is coupled to the gate of the second transistor. |
地址 |
TW |