发明名称 Training, power-gating, and dynamic frequency changing of a memory controller
摘要 A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.
申请公布号 US9104421(B2) 申请公布日期 2015.08.11
申请号 US201213561884 申请日期 2012.07.30
申请人 NVIDIA CORPORATION 发明人 Ahmad Sagheer;Riegelsberger Edward L.;Cheng Tony Yuhsiang;Moll Laurent Rene;Langendorf Brian Keith
分类号 G06F1/32;G06F9/44 主分类号 G06F1/32
代理机构 代理人
主权项 1. A method for managing a memory controller, the method comprising: selecting for entry a first low-power state from a plurality of available low-power states, wherein an available low-power state is a low-power state that is below a time threshold for transitioning; transitioning to the first low-power state from an original state; provided a wake event has not been received, entering the first low-power state when the transition to the first low-power state is complete.
地址 Santa Clara CA US