发明名称 Width scalable connector for high bandwidth IO interfaces
摘要 Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.
申请公布号 US9106217(B2) 申请公布日期 2015.08.11
申请号 US201113977050 申请日期 2011.12.06
申请人 Intel Corporation 发明人 Jaussi James E.;Pederson Bruce E.;Heck Howard L.;Mooney Stephen R.
分类号 H03K19/0175;H03K19/00;H01R13/66;H01R24/60;H01R25/00;H01R12/72 主分类号 H03K19/0175
代理机构 Jordan IP Law, LLC 代理人 Jordan IP Law, LLC
主权项 1. A male input/output (IO) interface comprising: a plurality of substrates, each substrate having a connection edge with a first side and a second side; at least one integrated butler coupled to at least one of the first side and the second side of each substrate; and a plurality of rows of contacts coupled to the first side of each substrate, wherein each row of contacts is stacked substantially parallel to the connection edge.
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