发明名称 |
Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit |
摘要 |
A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate including the polycrystalline silicon is then completed. |
申请公布号 |
US9105747(B2) |
申请公布日期 |
2015.08.11 |
申请号 |
US201012978730 |
申请日期 |
2010.12.27 |
申请人 |
Infineon Technologies AG |
发明人 |
Hierlemann Matthias;Sarma Chandrasekhar |
分类号 |
H01L27/108;H01L29/94;H01L21/8238;H01L21/84;H01L29/06;H01L29/78 |
主分类号 |
H01L27/108 |
代理机构 |
Slater & Matsil, L.L.P. |
代理人 |
Slater & Matsil, L.L.P. |
主权项 |
1. An integrated circuit, comprising:
a first trench disposed in a substrate; a second trench disposed in the substrate and separated from the first trench by a first interval; a first cavity disposed in the substrate within the first interval, wherein the first cavity is linked to a first sidewall of the first trench and wherein a second sidewall opposite to the first sidewall of the first trench is not linked to any cavity; a second cavity disposed in the substrate within the first interval, wherein the second cavity is linked to a first sidewall of the second trench and wherein a second sidewall opposite to the first sidewall of the second trench is not linked to any cavity; a dielectric material lining sidewalls and a bottom surface of each of the first cavity and the second cavity; polycrystalline silicon overlying the dielectric material within the first cavity and the second cavity, the polycrystalline silicon filling at least a part of the first trench and at least a part of the second trench; and a gate over a portion of the substrate between the first cavity and the second cavity. |
地址 |
Neubiberg DE |