Method for manufacturing a field effect transistor of a non-planar type

摘要

A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.

主权项

1. A method for manufacturing a field effect transistor of a non-planar type, comprising:
providing a substrate having an initially planar front main surface; providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures, wherein top surfaces of the shallow trench isolation structures and the fin structures are abutting on a common planar surface, and wherein sidewalls of the fin structures are fully concealed by the shallow trench isolation structures; forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface; forming dielectric spacer structures around the dummy gate structure; removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures; removing an upper portion from the fin structures in the gate trench; epitaxially regrowing the removed upper portion of the fin structures; and after removing the dummy gate structure and after epitaxially regrowing the removed upper portion of the fin structures, removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.