发明名称 |
Semiconductor device |
摘要 |
To provide a transistor which includes an oxide semiconductor and is capable of operating at high speed or a highly reliable semiconductor device including the transistor, a transistor in which an oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer, which is embedded in a base insulating layer and whose upper surface is at least partly exposed from the base insulating layer, and a wiring layer provided above the oxide semiconductor layer is electrically connected to the electrode layer or a part of a low-resistance region of the oxide semiconductor layer, which overlaps with the electrode layer. |
申请公布号 |
US9105732(B2) |
申请公布日期 |
2015.08.11 |
申请号 |
US201414483671 |
申请日期 |
2014.09.11 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Yamazaki Shunpei;Isobe Atsuo;Sasaki Toshinari |
分类号 |
H01L29/78;H01L29/786;H01L27/12 |
主分类号 |
H01L29/78 |
代理机构 |
Robinson Intellectual Property Law Office, P.C. |
代理人 |
Robinson Eric J.;Robinson Intellectual Property Law Office, P.C. |
主权项 |
1. A method for manufacturing a semiconductor device comprising the steps of:
forming a conductive layer embedded in a first insulating layer; forming an oxide semiconductor layer over and in contact with the conductive layer and the first insulating layer; forming a gate insulating layer over the oxide semiconductor layer; forming a gate electrode over the gate insulating layer; adding a dopant to the oxide semiconductor layer using the gate electrode as a mask, whereby the oxide semiconductor layer has a pair of low-resistance regions including the dopant; forming a second insulating layer over the oxide semiconductor layer and the gate electrode; forming a first wiring electrically connected to one of the pair of low-resistance regions through the second insulating layer; and forming a second wiring electrically connected to the other of the pair of low-resistance regions through the second insulating layer, wherein one of the pair of low-resistance regions is in contact with the conductive layer. |
地址 |
Atsugi-shi, Kanagawa-ken JP |