Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor

摘要

A method of making a split gate non-volatile memory (NVM) using a substrate includes etching a recess into an isolation region of an NVM region of the substrate and depositing a conductive layer and a capping layer. A select gate and a control gate are formed in the NVM region, and a dummy gate is formed in a logic region of the substrate. A portion of the capping layer is removed and a salicide block bi-layer is deposited and patterned to form a first opening that exposes a contact portion of the conductive layer over the recess. A silicided region is formed on the contact portion. The substrate is planarized to expose the dummy gate, which is replaced with a metal gate. A second opening is etched through a first interlayer dielectric deposited over the substrate to the silicided region. Contact metal is deposited into the second opening.

主权项

1. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a split gate non-volatile memory (NVM) cell in an NVM region of the substrate, the method comprising:
etching a recess into an isolation region of the substrate in the NVM region; depositing a polysilicon layer over the substrate, including over the recess; depositing a nitride layer over the polysilicon layer; forming a polysilicon select gate and a polysilicon control gate in the NVM region; forming a polysilicon gate in a logic region of the substrate; removing a portion of the nitride layer over the recess; depositing a salicide block bi-layer over the substrate, including over the recess; patterning the salicide block bi-layer to form a first opening in the salicide block bi-layer that exposes a contact portion of the polysilicon layer over the recess; forming a silicided region on the contact portion of the polysilicon layer over the recess within the first opening; planarizing the substrate to expose the polysilicon gate; replacing the polysilicon gate with a metal gate; depositing a first interlayer dielectric over the substrate; etching a second opening through the first interlayer dielectric to the silicided region; and depositing contact metal into the second opening.