发明名称 Enhanced clock and data recovery acquisition in the presence of large frequency offsets
摘要 A method for facilitating acquisition of a received reference clock signal in a CDR system includes steps of: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero.
申请公布号 US9106370(B1) 申请公布日期 2015.08.11
申请号 US201414495931 申请日期 2014.09.25
申请人 AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. 发明人 Srinivasa Sunil;Malipatil Amaresh V.;Mobin Mohammad Shafiul;Aziz Pervez Mirza;Kotagiri Shiva Prasad
分类号 H04L7/00;H03D3/24 主分类号 H04L7/00
代理机构 Sheridan Ross P.C. 代理人 Sheridan Ross P.C.
主权项 1. A method for facilitating acquisition of a received reference clock signal in a clock and data recovery (CDR) system, the method comprising: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero indicative of the CDR system acquiring the received reference clock signal.
地址 Singapore SG