Memory efficient implementation of LDPC decoder

摘要

A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

主权项

1. A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising:
receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering iterative process on each LLR bit in the LLR input bitstream without use of a front end memory buffer, comprising for each LLR bit in the LLR input bitstream:
determining a logical memory address for the LLR bit using the logical memory address determined for the last LLR bit except for the first LLR bit in the LLR input bitstream, anddetermining a physical memory address for the LLR bit from the logical memory address of determined for the LLR bit and dimension of the physical memory; storing each LLR bit in the LLR input bitstream in the physical memory space according to the determined physical memory address for the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.