Impedance calibration circuit and method

摘要

An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

主权项

1. A circuit, comprising:
a driver with an adjustable driver impedance; and an impedance calibration circuit, comprising:
a comparator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison;a programmable resistor coupled between the internal node and a chip ground line; andrespective resistor and capacitor components coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator;wherein the resistor and capacitor components are coupled to said chip ground line and configured for symmetric noise injection into the comparator from said chip ground line;a counter configured to generate first calibration codes in response to the output for application to control said programmable resistor; anda digital filter circuit configured to filter said first calibration codes to generate second calibration codes for application to control said adjustable driver impedance.