| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor device having a memory cell structure in which error is reduced without complicating the circuitry.SOLUTION: An inverter I1 (output is storage terminal Na) by an NMOS transistor N1 and a PMOS transistor P1 and an inverter I2 (output is storage terminal Nb) by an NMOS transistor N2 and a PMOS transistor P2 are cross connected, and NMOS transistors N3 and N4 are further connected, respectively, with the storage terminals Na and Nb. The NMOS transistors N1 and N3 having one electrodes connected with the storage terminal Na are formed separately in P well regions PW0 and PW1, and the NMOS transistors N2 and N4 having one electrodes connected with the storage terminal Nb are formed separately in P well regions PW1 and PW0. The P well regions PW0 and PW1 are formed on the opposite sides while holding an N well region NW therebetween. |
