POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR

摘要

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

主权项

1. A method comprising:
depositing a layer of conductive material over a first surface of a semiconductor material, wherein the semiconductor material comprises a plurality of transistors, and wherein each of the plurality of transistors includes a gate, a drain region, and a source region; and coupling gates of the plurality of transistors to each other with a mesh structure; wherein at least a portion of the mesh structure is positioned over the layer of conductive material, and wherein the layer of conductive material is positioned substantially between the mesh structure and the drain regions to thereby reduce gate-to-drain capacitance.