发明名称 AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS
摘要 A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
申请公布号 US2015221747(A1) 申请公布日期 2015.08.06
申请号 US201514688639 申请日期 2015.04.16
申请人 Texas Instruments Incorporated 发明人 PENDHARKAR Sameer;TIPIRNENI Naveen
分类号 H01L29/66;H01L29/201;H01L21/8232;H01L49/02;H01L27/06;H01L29/20;H01L29/205 主分类号 H01L29/66
代理机构 代理人
主权项 1. A method of forming a semiconductor device, comprising the steps of: forming a GaN FET by a process comprising the steps of: providing a substrate;forming an low-defect layer comprising gallium nitride over said substrate;forming a barrier layer comprising AlxGa1-xN one said low-defect layer, so that a two-dimensional electron gas is generated in said low-defect layer just below said barrier layer, said two-dimensional electron gas providing a conductive channel of said GaN FET;forming a gate over said barrier layer; andforming source and drain contacts to make tunneling connections to said two-dimensional electron gas; forming an overvoltage clamping component, and electrically coupling a first end of said overvoltage clamping component to a drain node of said GaN FET, said overvoltage clamping component being configured to conduct insignificant current when a voltage at said drain node is less than a safe voltage limit which is less than a breakdown voltage of said GaN FET; said overvoltage clamping component being further configured to conduct significant current when said voltage at said drain node of said GaN FET rises above said safe voltage limit; forming a voltage dropping component, electrically coupling a first end of said voltage dropping component to a second end of said overvoltage clamping component, and electrically coupling a second end of said voltage dropping component to a terminal for a bias potential which provides an off-state bias for said GaN FET, said voltage dropping component being configured to provide a voltage drop which increases as current from said overvoltage clamping component increases; and configuring said semiconductor device to turn on said GaN FET when said voltage drop across said voltage dropping component reaches a threshold value.
地址 Dallas TX US