| 发明名称 |
RECEIVER DESERIALIZER LATENCY TRIM |
| 摘要 |
A system and method for receiving includes an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream. A plurality of storage devices is configured to sample the serial stream. An output demultiplexer is configured to demultiplex the sampled serial stream into a plurality of output streams. A PRBS checker is configured to compare a PRBS pattern on the plurality of output streams with a predicted PRBS pattern. A phase rotator is configured to adjust a data control clock based upon the comparison of the PRBS checker to reduce latency in the receiver. |
| 申请公布号 |
US2015222377(A1) |
申请公布日期 |
2015.08.06 |
| 申请号 |
US201414172618 |
申请日期 |
2014.02.04 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Chieco Leonard R.;Keyser, III Frank R.;Sorna Michael A. |
| 分类号 |
H04J3/06;H04L7/04;H04L7/00 |
主分类号 |
H04J3/06 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A receiver, comprising:
an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream; a plurality of storage devices configured to sample the serial stream; an output demultiplexer configured to demultiplex the sampled serial stream into a plurality of output streams; a PRBS checker configured to compare a PRBS pattern on the plurality of output streams with a predicted PRBS pattern; and a phase rotator configured to adjust a data control clock based upon the comparison of the PRBS checker to reduce latency in the receiver. |
| 地址 |
Armonk NY US |
