| 发明名称 |
LOW INSERTION LOSS PACKAGE PIN STRUCTURE AND METHOD |
| 摘要 |
An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board. |
| 申请公布号 |
US2015222033(A1) |
申请公布日期 |
2015.08.06 |
| 申请号 |
US201414174697 |
申请日期 |
2014.02.06 |
| 申请人 |
Xilinx, Inc. |
发明人 |
Wu Paul Y.;Niazi Sarajuddin;Anderson Raymond E.;Ramlingam Suresh |
| 分类号 |
H01R12/71;H01R43/02 |
主分类号 |
H01R12/71 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A package assembly, comprising:
a package having a first portion and a second portion, wherein the first portion comprises a first plurality of pads with a first pad pitch size; and an insert electrically coupled to the second portion of the package, the insert having a second plurality of pads with a second pad pitch size, the first pad pitch size being larger than the second pad pitch size. |
| 地址 |
San Jose CA US |
