HIGH-BANDWIDTH DRAM USING INTERPOSER AND STACKING

摘要

Embodiments of the present disclosure provide a packaging arrangement that comprises an interposer and a system on chip (SoC) die disposed on the interposer. The packaging arrangement also comprises a plurality of memory dies stacked on one another to provide a stack of memory dies. A bottom memory die of the stack of memory dies is disposed on the substrate adjacent to the SoC die. Each memory die includes input/output (I/O) pads, wherein the I/O pads of a corresponding memory die are located on only one side of the corresponding memory die. The plurality of memory dies is stacked on one another such that all of the I/O pads are arranged along a same side of the stack of memory dies. The plurality of memory dies is also stacked such that all the I/O pads are exposed.

主权项

1. A packaging arrangement comprising:
an interposer; a system on chip (SoC) die disposed on the interposer; a plurality of memory dies stacked on one another to provide a stack of memory dies, wherein a bottom memory die of the stack of memory dies is disposed on the interposer adjacent to the SoC die, wherein each memory die includes input/output (I/O) pads, wherein the I/O pads of a corresponding memory die are located on only one side of the corresponding memory die, wherein the plurality of memory dies is stacked on one another such that all of the I/O pads are arranged along a same side of the stack of memory dies, and wherein the plurality of memory dies is stacked such that all the I/O pads are exposed.