MDLL/PLL HYBRID DESIGN WITH UNIFORMLY DISTRIBUTED OUTPUT PHASES

摘要

A circuit for generating a clock signal formed as a hybrid of a multiplying delay-locked loop (MDLL) and a phase locked loop (PLL). In one embodiment a chain of inverting delay multiplexers is connected in a ring configuration capable of operating as a ring oscillator, with a first delay multiplexer in the ring configured to substitute a feed-in clock signal for the feedback clock generated by the ring oscillator when an edge, either rising or falling, is received at the forwarded clock input. The first delay multiplexer may also be configured to interpolate between the phase of the feedback clock and the phase of the feed-in clock. The interpolation may be based on transistor channel widths and the value of a control signal, and results in behavior intermediate to that of an MDLL and that of a PLL.

主权项

1. A circuit to generate a local clock signal from a forwarded clock signal, the circuit comprising:
a plurality of delay multiplexers connected in a ring to generate the local clock signal, and a propagation delay control circuit, to adjust a propagation delay of each of the plurality of multiplexers.