发明名称 |
DOUBLE PHASE-LOCKED LOOP WITH FREQUENCY STABILIZATION |
摘要 |
A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks. |
申请公布号 |
US2015222276(A1) |
申请公布日期 |
2015.08.06 |
申请号 |
US201514595309 |
申请日期 |
2015.01.13 |
申请人 |
MICROSEMI SEMICONDUCTOR ULC |
发明人 |
Milijevic Slobodan |
分类号 |
H03L7/087;H03L7/099 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
1. A double phase-locked loop, comprising a first narrowband phase-locked loop including a first loop filter configured to reduce phase noise in a first input clock; a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source, said second clock having a frequency close to said first clock; said first phase-locked loop having a bandwidth at least an order of magnitude less than said second phase-locked loop; and a coupler configured to couple said first and second phase-locked loops to provide a common output whereby said second phase locked loop stabilizes said first phase locked loop. |
地址 |
Kanata CA |