| 发明名称 |
Computer Processor Employing Phases of Operations Contained in Wide Instructions |
| 摘要 |
A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each having an encoding that represents a plurality of different operations. The plurality of different operations of the given wide instruction are logically organized into a number of phases having a predefined ordering such that at least one operation of the given wide instruction produces data that is consumed by at least one other operation of the given wide instruction. In certain circumstances where stalling is absent, the plurality of different operations of the phases of the given wide instruction can be issued for execution by the instruction processing pipeline over a plurality of consecutive machine cycles. |
| 申请公布号 |
US2015220343(A1) |
申请公布日期 |
2015.08.06 |
| 申请号 |
US201514667404 |
申请日期 |
2015.03.24 |
| 申请人 |
Mill Computing, Inc. |
发明人 |
Godard Roger Rawson;Kahlich Arthur David;Yost David Arthur;Mirolo Sebastien Paul Maurice |
| 分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A computer processor comprising:
an instruction processing pipeline that processes a sequence of wide instructions, wherein each given wide instruction has an encoding that represents a plurality of different operations, wherein the plurality of different operations of the given wide instruction are logically organized into a number of phases having a predefined ordering such that at least one operation of the given wide instruction produces data that is consumed by at least one other operation of the given wide instruction. |
| 地址 |
Palo Alto CA US |
