FLOATING GUARD RING FOR HV INTERCONNECT

摘要

Aspects of the present disclosure describe an integrated circuit comprises a substrate of a first conductivity type semiconductor, a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate, a driver circuit, an electrically conductive interconnect structure formed over the semiconductor layer and electrically connected to the driver circuit at one end, at least one guard structure formed in the semiconductor layer and under the interconnect structure and a well region of the first conductivity type semiconductor formed in a top portion of the semiconductor layer, between the driver circuit and the at least one guard structure and under the interconnect structure. The guard structure is electrically floating. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

主权项

1. An integrated circuit, comprising:
a substrate of a first conductivity type semiconductor; a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate; a driver circuit including a first doped region of a second conductivity type semiconductor disposed in the semiconductor layer; an electrically conductive interconnect structure formed over the semiconductor layer and electrically connected to the driver circuit at one end; at least one guard structure formed in the semiconductor layer and under the interconnect structure, wherein the at least one guard structure is electrically floating; and a well region of the first conductivity type semiconductor formed in a top portion of the semiconductor layer and under the interconnect structure, wherein the well region is disposed between the driver circuit and the at least one guard structure and wherein the well region is doped heavier than the semiconductor layer.