METALLIZATION SCHEME FOR INTEGRATED CIRCUIT

摘要

For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. Parallel lines in the same metal level can be rotated with respect to one another in adjacent regions, for example to better interface with driver circuitry with orthogonal orientations in the different regions.

主权项

1. An integrated circuit having a memory array, comprising:
a first driver region comprising a plurality of first parallel conductive lines formed at a first vertical metal level and extending in a first direction, wherein first drivers are formed below the first vertical metal level within the first driver region; and a second driver region laterally bordering the first driver region and comprising a plurality of second parallel conductive lines formed at the first vertical metal level and extending in a second direction crossing the first direction, wherein second drivers are formed below the first vertical metal level within the second driver region, wherein the first drivers are configured to drive first electrode lines of the memory array and the second drivers are configured to drive second electrode lines of the memory array, the first and second electrode lines extending in different directions.