发明名称 MAGNETIC MEMORY DEVICE
摘要 The magnetic memory device includes a plurality of source lines arranged in parallel in a second direction orthogonal to a first direction while extending in the first direction on a substrate, a plurality of word lines arranged in parallel in the first direction while extending in the second direction on the substrate, a plurality of bit lines arranged in parallel in the second direction while extending in the first direction on the substrate to alternate with the plurality of source lines, and a plurality of active regions arranged to extend at an oblique angle with respect to the first direction and arranged so that one memory cell is selected when one of the plurality of word lines and one of the plurality of source lines or the plurality of bit lines are selected.
申请公布号 US2015221699(A1) 申请公布日期 2015.08.06
申请号 US201514599064 申请日期 2015.01.16
申请人 Samsung Electronics Co., Ltd. 发明人 LEE Jae-kyu;SUH Ki-Seok
分类号 H01L27/22;H01L43/08;H01L43/02 主分类号 H01L27/22
代理机构 代理人
主权项 1. A magnetic memory device comprising: a plurality of active regions defined on a substrate by an isolation film, the plurality of active regions are extended in one direction so that a first region and a second region are provided at both ends of each of the plurality of active regions, arranged so that the one direction forms an oblique angle with respect to a first direction, and arranged in parallel in a second direction intersecting the first direction; a plurality of word lines arranged in parallel in the first direction while extending in the second direction on the substrate across corresponding ones of the plurality of active regions arranged in the second direction; a plurality of source lines arranged in parallel in the second direction while extending in the first direction and commonly and electrically connected to the first regions of corresponding ones of the plurality of active regions arranged in the first direction; a plurality of variable resistance structures arranged in the first and second directions to correspond to the plurality of active regions, respectively, and electrically connected to the second regions of corresponding ones of the plurality of active regions; and a plurality of bit lines arranged in parallel in the second direction while extending in the first direction to alternate with the plurality of source lines and commonly and electrically connected to corresponding ones of the plurality of variable resistance structures arranged in the first direction, wherein, when a source line adjacent to a first bit line that is one of the plurality of bit lines below the first bit line in the second direction is referred to as a lower source line and a source line adjacent to the first bit line above the first bit line in the second direction is referred to as an upper source line, in the first direction, the plurality of active regions are alternately arranged between the first bit line and the lower source line and between the first bit line and the upper source line.
地址 Suwon-Si KR